 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ADVANCE Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters (ADCs) CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs FEATURES n n n General Description The CDK1308 is a high performance ultra low power analog-to-digital converter (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. Two idle modes with fast startup times exist. The entire chip can either be put in Standby Mode or Power Down mode. The two modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK1308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave, and CMOS clock inputs. 10-bit resolution 20/40/65/80MSPS max sampling rate Ultra-Low Power Dissipation: 15/25/38/46mW 61.6dB SNR at 8MHz FIN Internal reference circuitry 1.8V core supply voltage 1.7 - 3.6V I/O supply voltage Parallel CMOS output 40-pin QFN package Pin compatible with CDK1307 n n n n n n n APPLICATIONS n n n n Medical Imaging Portable Test Equipment Digital Oscilloscopes IF Communication Functional Block Diagram Rev 0.1 10 Ordering Information Part Number CDK1308AILP40 CDK1308BILP40 CDK1308CILP40 CDK1308DILP40 Speed 20MSPS 20MSPS 65MSPS 80MSPS Package QFN-40 QFN-40 QFN-40 QFN-40 Pb-Free Yes Yes Yes Yes RoHS Compliant Yes Yes Yes Yes Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Packaging Method Tray Tray Tray Tray Moisture sensitivity level for all parts is MSL-3. (c)2008 CADEKA Microcircuits LLC www.cadeka.com ADVANCE Data Sheet Pin Configuration CM_EXTBC_0 CM_EXTBC_1 QFN-40 SLP_N OVDD OVDD D_9 D_8 D_7 D_6 D_5 CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs 40 39 38 37 36 35 34 33 32 DVSS CM_EXT AVDD AVDD IP IN AVDD DVDDCLK CLKP CLKN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 31 30 29 28 D_4 D_3 D_2 CLK_EXT OVDD OVDD ORNG D_1 D_0 NC CDK1308 QFN-40 27 26 25 24 23 22 21 DFRMT OE_N OVDD OVDD NC DVDD Pin Assignments Pin No. 0 1, 11, 16 2 3, 4, 7 5, 6 8 9 10 12 13 14 15 17, 18, 25, 26, 36, 37 19 20 21 22 Pin Name VSS DVDD CM_EXT AVDD IP, IN DVDDCLK CLKP CLKN CLK_EXT_EN DFRMT PD_N OE_N OVDD NC NC NC D_0 Output Data Description Ground connection for all power domains. Exposed pad Digital and I/O-ring pre driver supply voltage, 1.8V Common Mode voltage output Analog supply voltage, 1.8V Analog input (non-inverting, inverting) Clock circuitry supply voltage, 1.8V Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave) Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground CLK_EXT signal enabled when low (zero). Tristate when high. Data format selection. 0: Offset Binary, 1: Two's Complement Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up always apply Power Down mode before using Active Mode to reset chip. Output Enable. Tristate when high I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V CLK_EXT_EN DVDD PD_N NC Rev 0.1 (c)2008 CADEKA Microcircuits LLC www.cadeka.com 2 ADVANCE Data Sheet Pin Assignments (Continued) Pin No. 23 24 27 28 29 30 31 32 33 34 35 38, 39 Pin Name D_1 ORNG CK_EXT D_2 D_3 D_4 D_5 D_6 D_7 D_8 D_9 CM_EXTBC_1, CM_EXTBC_0 SLP_N Description Output Data Out of Range flag. High when input signal is out of range CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Output clock signal for data synchronization. CMOS levels Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data (MSB) Bias control bits for the buffer driving pin CM_EXT 00: OFF 10: 500A 10: 50A 11: 1mA 40 Sleep Mode when low Rev 0.1 (c)2008 CADEKA Microcircuits LLC www.cadeka.com 3 ADVANCE Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Parameter AVDD DVDD AVSS, DVSSCK, DVSS, OVSS OVDD CLKP, CLKN Analog inputs and outpts (IPx, INx) Digital inputs Digital outputs Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max +2.3 +2.3 +0.3 +3.9 +3.9 +2.3 +3.9 +3.9 Unit V V V V V V V V Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Min -60 TBD Typ Max TBD +150 Unit C C C ESD Protection Product Human Body Model (HBM) Charged Device Model (CDM) QFN-40 2kV TBD Recommended Operating Conditions Parameter Operating Temperature Range Min -40 Typ Max +85 Unit C Rev 0.1 (c)2008 CADEKA Microcircuits LLC www.cadeka.com 4 ADVANCE Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise noted) Symbol DC Accuracy Parameter No Missing Codes Offset Error Gain Error Conditions Min Typ Guaranteed Max Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Midscale offset Full scale range deviation from typical -6 -0.3 -0.6 TBD 6 0.3 0.6 VAVDD/2 mV %FS LSB LSB V VCM +0.1 V Vpp pF MHz DNL INL VCMO Differential Non-Linearity Integral Non-Linearity Common Mode Voltage Output Input Common Mode Full Scale Range Input Capacitance Bandwidth Analog input common mode voltage Differential input voltage range Differential input capacitance Input bandwidth, full power Supply voltage to all 1.8V domain pins. See Pin Configuration and Description Output driver supply voltage (OVDD). Must be higher than or equal to Core Supply Voltage (VOVDD VOCVDD) Analog Input VCMI VFSR VCM -0.1 2.0 1.8 500 1.7 1.7 1.8 2.5 2.0 3.6 Power Supply AVDD, DVDD OVDD Core Supply Voltage I/O Supply Voltage V V Rev 0.1 (c)2008 CADEKA Microcircuits LLC www.cadeka.com 5 ADVANCE Data Sheet Electrical Characteristics - CDK1308A (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 2MHz Min Typ 61.7 61.6 61.6 61.6 61.7 61.6 60.5 61.6 84.1 85.5 70.3 87.5 -88.8 -89.5 -95.9 -91.4 -89.5 -90.5 -70.3 -89.7 10.0 9.9 9.8 9.9 5.6 Max Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW W mW MSPS 15 MSPS SNR Signal to Noise Ratio FIN = 8MHz FIN FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 20MHz SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 20 1.0 1.7 1.2 10.1 4.8 14.9 9.9 7.7 Rev 0.1 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Clock Inputs Max. Conversion Rate Min. Conversion Rate (c)2008 CADEKA Microcircuits LLC www.cadeka.com 6 ADVANCE Data Sheet Electrical Characteristics - CDK1308B (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 2MHz Min Typ 61.6 61.6 61.6 61.5 61.6 61.6 61.2 61.4 78.8 82.3 72.0 82.5 -87.9 -92.0 -84.8 -88.8 -81.8 -85.7 -72.0 -83.9 9.9 9.9 9.9 9.9 9.3 Max Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW W mW MSPS 20 MSPS SNR Signal to Noise Ratio FIN = 8MHz FIN FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 30MHz SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 40 1.7 3.1 2.2 16.7 8.6 25.3 9.7 11.3 Rev 0.1 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Clock Inputs Max. Conversion Rate Min. Conversion Rate (c)2008 CADEKA Microcircuits LLC www.cadeka.com 7 ADVANCE Data Sheet Electrical Characteristics - CDK1308C (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 8MHz Min Typ 61.6 61.6 61.5 61.3 61.6 61.6 60.4 61.1 80.6 85.6 66.4 76.9 -91.4 -93.0 -83.8 -90.7 -80.6 -86.4 -66.4 -76.9 9.9 9.9 9.7 9.9 13.8 Max Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW W mW MSPS 40 MSPS SNR Signal to Noise Ratio FIN = 20MHz FIN FS/2 FIN = 40MHz FIN = 8MHz FIN = 20MHz FIN FS/2 FIN = 40MHz FIN = 8MHz FIN = 20MHz FIN FS/2 FIN = 40MHz FIN = 8MHz FIN = 20MHz FIN FS/2 FIN = 40MHz FIN = 8MHz FIN = 20MHz FIN FS/2 FIN = 40MHz FIN = 8MHz FIN = 20MHz FIN FS/2 FIN = 40MHz SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 65 2.6 4.9 3.4 24.8 13.2 38.0 9.3 15.7 Rev 0.1 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Clock Inputs Max. Conversion Rate Min. Conversion Rate (c)2008 CADEKA Microcircuits LLC www.cadeka.com 8 ADVANCE Data Sheet Electrical Characteristics - CDK1308D (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 8MHz Min Typ 61.6 61.2 61.3 61.3 61.3 60.7 61.0 58.7 74.8 73.9 74.7 61.7 -88.5 -95.0 -88.9 -79.0 -74.8 -75.0 -74.7 -61.7 9.9 9.8 9.8 9.5 16.5 Max Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW W mW MSPS 65 MSPS SNR Signal to Noise Ratio FIN = 20MHz FIN = 30MHz FIN FS/2 FIN = 8MHz FIN = 20MHz FIN = 30MHz FIN FS/2 FIN = 8MHz FIN = 20MHz FIN = 30MHz FIN FS/2 FIN = 8MHz FIN = 20MHz FIN = 30MHz FIN FS/2 FIN = 8MHz FIN = 20MHz FIN = 30MHz FIN FS/2 FIN = 8MHz FIN = 20MHz FIN = 30MHz FIN FS/2 SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 80 3.3 5.9 4.1 29.7 16.2 45.9 9.1 18.3 Rev 0.1 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Clock Inputs Max. Conversion Rate Min. Conversion Rate (c)2008 CADEKA Microcircuits LLC www.cadeka.com 9 ADVANCE Data Sheet Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted) Symbol Clock Inputs Parameter Duty Cycle Compliance Input Range Input Common Mode Voltage Input Capacitance Conditions Min 20 Typ Max 80 200 800 VOVDD -0.3 Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs % high mVpp mVpp V pF CMOS, LVDS, LVPECL, Sine Wave Differential input swing Differential input swing, sine wave clock input Keep voltages within ground and voltage of OVDD Differential From Power Down Mode to Active Mode References has reached 99% of final value From Sleep Mode to Active Mode 0.5 1 0.8 <0.5 12 5pF load on output bits (see timing diagram) 10pF load on output bits (see timing diagram) See timing diagram VOVDD 3.0V VOVDD = 1.7V - 3.0V VOVDD 3.0V VOVDD = 1.7V - 3.0V 2 0.8 * VOVDD 0 0 -10 -10 3 -0.1 +VOVDD 0.1 Post-driver supply voltage equal to pre-driver supply voltage VOVDD = VOCVDD Post-driver supply voltage above 2.25V (1) 10 5 0.8 0.2 * VOVDD 10 10 2 4 TBD -200 -800 0.3 1.7 Timing TPD TSLP TOVR TAP Start Up Time from Power Down Start Up Time from Sleep Out Of Range Recovery Time Aperture Delay Aperture Jitter Pipeline Delay Output Delay Output Delay Relative to CLK_EXT 900 clk cycles s clk cycles ns ps clk cycles ns ns ns V V V V A A pF V V pF pF RMS TLAT TD TDC Logic Inputs VIH VIL IIH IIL CI High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Input Capacitance High Level Output Voltage Low Level Output Voltage Max Capacitive Load Logic Outputs VOH VOL CL Note: (1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum. Rev 0.1 (c)2008 CADEKA Microcircuits LLC www.cadeka.com 10 ADVANCE Data Sheet N+3 N+2 N N+1 N+4 N+5 CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs N-13 CLK_EXT Figure 1. Timing Diagram Recommended Usage Analog Input The analog inputs to the CDK1308 is a switched capacitor track-and-hold amplifier optimized for differential operation. Operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. The CM_EXT pin provides a voltage suitable as common mode voltage reference. The internal buffer for the CM_EXT voltage can be switched off, and driving capabilities can be changed by using the CM_EXTBC control input. Figure 2 shows a simplified drawing of the input network. The signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. A small external resistor (e.g. 22) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. A small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. The resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. DC-Coupling Figure 3 shows a recommended configuration for DCcoupling. Note that the common mode input voltage must be controlled according to specified values. Preferably, the CM_EXT output should be used as a reference to set the common mode voltage. The input amplifier could be inside a companion chip or it could be a dedicated amplifier. Several suitable single ended to differential driver amplifiers exist in the market. The system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with the CDK1308 input specifications. Rev 0.1 pF Figure 3. DC-Coupled Input Detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in Figure 3 must be varied according to the recommendations for the driver. AC-Coupling Figure 2. Input Configuration (c)2008 CADEKA Microcircuits LLC A signal transformer or series capacitors can be used to make an AC-coupled input network. Figure 4 shows www.cadeka.com 11 ADVANCE Data Sheet a recommended configuration using a transformer. Make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. The bandwidth should exceed the sampling rate of the ADC with at least a factor of 10. It is also important to keep phase mismatch between the differential ADC inputs small for good HD2 performance. This type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. If the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kickbacks from the ADC will also travel along this distance. If these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the ADC input. This could reduce the ADC performance. To avoid this effect, the source must effectively terminate the ADC kick-backs, or the traveling distance should be very short. If this problem could not be avoided, the circuit in Figure 6 can be used. Note that startup time from Sleep Mode and Power Down Mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. If the input signal has a long traveling distance, and the kickbacks from the ADC not are effectively terminated at the signal source, the input network of Figure 6 can be used. The configuration is designed to attenuate the kickback from the ADC and to provide an input impedance that looks as resistive as possible for frequencies below Nyquist. Values of the series inductor will however depend on board design and conversion rate. In some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pF) may improve ADC performance further. This capacitor attenuate the ADC kick-back even more, and minimize the kicks traveling towards the source. However, the impedance match seen into the transformer becomes worse. CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs 33 RT 47 1:1 120nH 33 optional RT 68 120nH 220 pF 33 33 Figure 4. Transformer-Coupled Input Figure 5 shows AC-coupling using capacitors. Resistors from the CM_EXT output, RCM, should be used to bias the differential input signals to the correct voltage. The series capacitor, CI, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. Figure 6. Alternative Input Network Rev 0.1 Clock Input And Jitter Considerations Typically high-speed ADCs use both clock edges to generate internal timing signals. In the CDK1308 only the rising edge of the clock is used. Hence, input clock duty cycles between 20% and 80% is acceptable. The input clock can be supplied in a variety of formats. The clock pins are AC-coupled internally, and hence a wide common mode voltage range is accepted. Differential clock sources as LVDS, LVPECL or differential sine wave can be connected directly to the input pins. For CMOS inputs, the CLKN pin should be connected to ground, and the CMOS clock signal should be connected to CLKP. For differential sine wave clock input the amplitude must be at least 800mVpp. 12 pF Figure 5. AC-Coupled Input (c)2008 CADEKA Microcircuits LLC www.cadeka.com ADVANCE Data Sheet The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in the equation below: SNRjitter = 20 * log (2 * * FIN * t) where FIN is the signal frequency, and t is the total rms jitter measured in seconds. The rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. For applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. This can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. The jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter performance is obtained with LVDS or LVPECL clock with fast edges. CMOS and sine wave clock inputs will result in slightly degraded jitter performance. If the clock is generated by other circuitry, it should be retimed with a low jitter master clock as the last operation before it is applied to the ADC clock input. The voltage on the OVDD pin set the levels of the CMOS outputs. The output drivers are dimensioned to drive a wide range of loads for OVDD above 2.25V, but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. In applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the ADC chip. The timing is described in the Timing Diagram section. Note that the load or equivalent delay on CK_EXT always should be lower than the load on data outputs to ensure sufficient timing margins. The digital outputs can be set in tristate mode by setting the OE_N signal high. The CDK1308 employs digital offset correction. This means that the output code will be 4096 with shorted inputs. However, small mismatches in parasitics at the input can cause this to alter slightly. The offset correction also results in possible loss of codes at the edges of the full scale range. With no offset correction, the ADC would clip in one end before the other, in practice resulting in code loss at the opposite end. With the output being centered digitally, the output will clip, and the out of range flags will be set, before max code is reached. When out of range flags are set, the code is forced to all ones for over-range and all zeros for under-range. CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Data Format Selection The output data are presented on offset binary form when DFRMT is low (connect to OVSS). Setting DFRMT high (connect to OVDD) results in 2's complement output format. Details are shown in Table 1 below. Rev 0.1 Digital Outputs Digital output data are presented on parallel CMOS form. Table 1: Data Format Description for 2Vpp Full Scale Range Differential Input Voltage (IP - IN) Output data: D_9 : D_0 (DFRMT = 0, offset binary) Output Data: D_9 : D_0 (DFRMT = 1, 2's complement) 1.0 V +0.24mV -0.24mV -1.0V 11 1111 1111 10 0000 0000 01 1111 1111 00 0000 0000 01 1111 1111 00 0000 0000 11 1111 1111 10 0000 0000 (c)2008 CADEKA Microcircuits LLC www.cadeka.com 13 ADVANCE Data Sheet Reference Voltages The reference voltages are internally generated and buffered based on a bandgap voltage reference. No external decoupling is necessary, and the reference voltages are not available externally. This simplifies usage of the ADC since two extremely sensitive pins, otherwise needed, are removed from the interface. tributes to the Power Down Dissipation. The startup time from this mode is longer than for Sleep Mode as all references need to settle to their final values before normal operation can resume. The SLP_N signal can be used to set the full chip in Sleep Mode. In this mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time. However, Sleep Mode represents a significant reduction in supply current, and it can be used to save power even for short idle periods. The input clock should be kept running in all idle modes. However, even lower power dissipation is possible in Power Down mode if the input clock is stopped. In this case it is important to start the input clock prior to enabling active mode. CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Operational Modes The operational modes are controlled with the PD_N and SLP_N pins. If PD_N is set low, all other control pins are overridden and the chip is set in Power Down mode. In this mode all circuitry is completely turned off and the internal clock is disabled. Hence, only leakage current con- Mechanical Dimensions QFN-40 Package D D2 Pin 1 ID - Dia. 0.5 (Top Side) 1.14 Pin 1 ID - Dia. R F A G A3 0.45 Pin 0 Exposed Pad A1 Symbol A A1 A2 A3 b D D1 D2 L e 1 Min - 0.001 - 0.008 0.156 0.012 0 0.008 0.0096 0.004 F G R Inches Typ - 0.0004 0.023 0.008 REF 0.010 0.236 BSC 0.226 BSC 0.162 0.016 0.020 BSC - - 0.0168 0.008 Max 0.035 0.002 0.028 0.013 Min - 0.00 - 0.2 0.167 0.020 12 - 0.024 - 3.95 0.3 0 0.2 0.24 0.1 Millimeters Typ - 0.01 0.65 0.2 REF 0.25 6.00 BSC 5.75 BSC 4.10 0.4 0.50 BSC - - 0.42 0.2 Max 0.9 0.05 0.7 0.32 4.25 0.5 12 - 0.6 - NOTE: D D2 D1 Package dimensions in millimeter unless otherwise noted. Rev 0.1 1 L e b A2 For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2008 by CADEKA Microcircuits LLC. All rights reserved. A m p l i fy t h e H u m a n E x p e r i e n c e designed by |
Price & Availability of CDK1308CILP40
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |